Title :
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
Author :
Galiay, J. ; Crouzet, Y. ; Vergniault, M.
Author_Institution :
Société pour l´´Etude et la Fabrication de Circuits Intégrés Spéciaux (EFCIS)
fDate :
6/1/1980 12:00:00 AM
Abstract :
At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.
Keywords :
Failure characterization; fault models; test sequences generation; testability improvement; testing procedures; Circuit faults; Circuit testing; Delay; Electric variables; Energy consumption; Integrated circuit testing; Large scale integration; Logic testing; Production; Voltage; Failure characterization; fault models; test sequences generation; testability improvement; testing procedures;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1980.1675614
