DocumentCode
1142400
Title
A Recovery Cache for the PDP-11
Author
Lee, P.A. ; Ghani, N. ; Heron, K.
Author_Institution
Computing Laboratory, University of Newcastle- upon-Tyne
Issue
6
fYear
1980
fDate
6/1/1980 12:00:00 AM
Firstpage
546
Lastpage
549
Abstract
Backward error recovery is an integral part of the recovery block scheme that has been advanced as a method for providing tolerance against faults in software; the recovery cache has been proposed as a mechanism for providing this error recovery capability. This correspondence describes a recovery cache that has been built for the PDP-11 family of machines. This recovery cache has been designed to be an "add-on" unit which requires no hardware alterations to the host CPU but which intersects the bus between the CPU and the memory modules. Specially designed hardware enables concurrent operation of the recovery cache and the host system, and aims to minimize the overheads imposed on the host.
Keywords
Backward error recovery; fault-tolerant software; recovery blocks; Central Processing Unit; Computer architecture; Computer errors; Fault tolerance; Fault tolerant systems; Hardware; Laboratories; Redundancy; Software systems; Backward error recovery; fault-tolerant software; recovery blocks;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1980.1675618
Filename
1675618
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