DocumentCode :
1142513
Title :
A Novel Biasing Technique for Addressable Parametric Arrays
Author :
Smith, Brad ; Arriordaz, Alexandre ; Kolagunta, Venkat ; Schmidt, Jeff ; Shroff, Mehul
Author_Institution :
Freescale Semicond., Austin, TX
Volume :
22
Issue :
1
fYear :
2009
Firstpage :
134
Lastpage :
145
Abstract :
Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence.
Keywords :
CMOS integrated circuits; field effect transistor switches; 1 times 32 arrays; 4 times 32 arrays; CMOS pass gates; MOSFET; addressable parametric arrays; biasing technique; parasitic leakage; switches; Active matrix addressing; Current measurement; Geometry; Isolation technology; Joining processes; MOSFETs; Predictive models; Probes; Switches; Testing; MOSFET array; parametric test; probe pads; source biasing; test structure design; variability;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2008.2010745
Filename :
4773477
Link To Document :
بازگشت