DocumentCode :
1143047
Title :
Efficient Function Implementation for Bit-Serial Parallel Processors
Author :
Reeves, Anthony P. ; Bruner, John D.
Author_Institution :
School of Electrical Engineering, Purdue University
Issue :
9
fYear :
1980
Firstpage :
841
Lastpage :
844
Abstract :
Parallel processors with bit-serial processing elements (PE´s) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described for generating efficient programs to implement arbitrary functions on bit-serial-arithmetic processors. This scheme is based on logic design methodology and involves designing a logic network to realize a desired function. The parallel processor is then used to efficiently simulate a set of these networks. Heuristic design algorithms are used to generate the logic networks; several algorithms are described and compared with some benchmark functions. Several efficient PE designs are described and analyzed.
Keywords :
Binary array processing; Reed-Muller canonic form; bit-serial arithmetic; logic design algorithms; parallel processing; two-input gate networks; universal logic modules; Algorithm design and analysis; Arithmetic; Array signal processing; Boolean functions; Character generation; Design methodology; Heuristic algorithms; Logic design; Logic gates; Parallel processing; Binary array processing; Reed-Muller canonic form; bit-serial arithmetic; logic design algorithms; parallel processing; two-input gate networks; universal logic modules;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1980.1675685
Filename :
1675685
Link To Document :
بازگشت