Title :
Design for Autonomous Test
Author :
McCluskey, Edward J. ; Nesbat, Saied Bozorgui
Author_Institution :
Center for Reliable Computing, Computer Systems Laboratory, Departments of Computer Science and Electrical Engineering, Stanford University
Abstract :
A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
Keywords :
Built-in test; CMOS testing; VLSI testing; design for testability; exhaustive testing; partitioning; self-test; signature analysis; stuck- open faults; test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integrated circuit testing; Military computing; Sequential analysis; System testing; Test pattern generators; Very large scale integration; Built-in test; CMOS testing; VLSI testing; design for testability; exhaustive testing; partitioning; self-test; signature analysis; stuck- open faults; test pattern generation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1981.1675717
