Abstract :
IEEE Micro editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.
Keywords :
CMOS; Integrated microarchitectures; presilicon modeling; scalable on-chip interconnection network; special purpose accelerators; Analytical models; Computational modeling; Computer architecture; Microarchitecture; Multicore processing; Network-on-a-chip; Power system reliability; Research and development; Semiconductor device modeling; System-on-a-chip; CMOS; Integrated microarchitectures; presilicon modeling; scalable on-chip interconnection network; special purpose accelerators;
