Title :
Dynamic zero-sensitivity scheme for low-power cache memories
Author :
Chang, Yen-Jen ; Lai, Feipei
Author_Institution :
Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
Abstract :
A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip´s total power consumption. Because most bit values read from the cache are 0´s, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.
Keywords :
SRAM chips; cache storage; low-power electronics; microprocessor chips; power consumption; DZS scheme; SRAM cell; dynamic zero-sensitivity scheme; low-power cache memory; power consumption; Data mining; Degradation; Differential amplifiers; Energy consumption; Microprocessors; Random access memory; Semiconductor device manufacture; Stability; Virtual manufacturing; Voltage; Bitlines; Cache; DZS; Dynamic zero-sensitivity; Power reduction;
Journal_Title :
Micro, IEEE
