Title :
Optimal Layout of CMOS Functional Arrays
Author :
Uehara, Takao ; Vancleemput, William M.
Author_Institution :
Computer Science Laboratory, Fujitsu Laboratories
fDate :
5/1/1981 12:00:00 AM
Abstract :
Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.
Keywords :
CMOS circuit design; CMOS functional arrays; LSI design automation; LSI layout; computer-aided design; design automation; Circuit synthesis; Circuit topology; Design automation; FETs; Laboratories; Large scale integration; Logic arrays; Logic functions; Network synthesis; Network topology; CMOS circuit design; CMOS functional arrays; LSI design automation; LSI layout; computer-aided design; design automation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1981.1675787
