Title :
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
Author :
Hong, Se June ; Ostapko, Daniel L.
Author_Institution :
IBM T. J. Watson Research Center
fDate :
5/1/1981 12:00:00 AM
Abstract :
A simple procedure to produce a minimum length test set for a parity network is presented. If M is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line.
Keywords :
EX-OR gate; optimum testing; parity tree; Circuit faults; Circuit testing; Computer errors; Computer networks; Cost function; Delay effects; Error correction; Input variables; Logic testing; Test pattern generators; EX-OR gate; optimum testing; parity tree;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1981.1675793
