Capacitance calculation of IC packages using the finite element method and planes of symmetry

Author

Chou, Tai-Yu ; Cendes, Zoltan J.

Author_Institution

Adv. Package Dev. Group, LSI Logic Corp., Fremont, CA, USA

Volume

13

Issue

9

fYear

1994

fDate

9/1/1994 12:00:00 AM

Firstpage

1159

Lastpage

1166

Abstract

Finite element techniques are presented for determining the capacitance of three-dimensional interconnection structures. Results are presented for two typical intergrated circuits packages: the plastic leaded chip carrier (PLCC) and the dual in-line package (DIP). The symmetry of the capacitance matrix in the package is described and a set of formulas is presented to take advantage of this symmetry in capacitance calculation. This leads to the reduction in CPU time and memory usage and better converged solution

Keywords

capacitance; electronic engineering computing; finite element analysis; integrated circuit technology; matrix algebra; packaging; DIP; FEM; IC packages; PLCC; capacitance calculation; capacitance matrix; dual in-line package; finite element method; intergrated circuits packages; planes of symmetry; plastic leaded chip carrier; three-dimensional interconnection structures; Capacitance; Central Processing Unit; Equations; Finite difference methods; Finite element methods; Geometry; Integrated circuit interconnections; Integrated circuit packaging; Plastic packaging; Sparse matrices;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.310904

Filename

310904