A Layout System for the Random Logic Portion of an MOS LSI Chip

Author

Shirakawa, Isao ; Okuda, Noboru ; Harada, Takashi ; Tani, Sadahiro ; Ozaki, Hiroshi

Author_Institution

Departrment of Electronic Engineering, Osaka University

Issue

8

fYear

1981

Firstpage

572

Lastpage

581

Abstract

The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.

Keywords

Complex gate; MOS ratioless circuit one-dimensional gate array problem; computer-aided design (CAD); large-scale integration (LSI); layout; minimization of Boolean exeression; random logic; Boolean functions; Clocks; Computer displays; Design automation; Large scale integration; Logic arrays; Logic circuits; Logic design; Logic gates; Random access memory; Complex gate; MOS ratioless circuit one-dimensional gate array problem; computer-aided design (CAD); large-scale integration (LSI); layout; minimization of Boolean exeression; random logic;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1981.1675842

Filename

1675842