• DocumentCode
    1144692
  • Title

    Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits

  • Author

    Savir, Jacob

  • Author_Institution
    IBM T. J. Watson Research Center
  • Issue
    8
  • fYear
    1981
  • Firstpage
    606
  • Lastpage
    608
  • Abstract
    In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design.
  • Keywords
    Inversion parity; reconvergent fan-out; unate function; Boolean functions; Circuit faults; Circuit testing; Combinational circuits; Design methodology; Jacobian matrices; Joining processes; Logic design; Logic testing; Pins; Inversion parity; reconvergent fan-out; unate function;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1981.1675849
  • Filename
    1675849
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1144692