An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H

Author

Ishikawa, Masayuki ; Tsukahara, Tsuneo

Author_Institution

NTT LSI Lab., Kanagawa, Japan

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1485

Lastpage

1491

Abstract

An 8-b video-rate subranging analog-to-digital (A/D) converter with pipelined wideband sample-and-hold (S/H) amplifiers is described. The chip architecture is based on a newly developed subranging technique that combines a digital-to-analog subconverter and a subtractor in one body. The development of a bandwidth enhancement technique for the S/H amplifier yields a wide effective resolution bandwidth using 1-μm CMOS technology. An effective resolution bandwidth of 25 MHz was achieved, as well as a small input capacitance of 1.5 pF, due to the high performance of the S/H circuit developed

Keywords

CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; 1 micron; 1.5 pF; 25 MHz; 50 MHz; 8 bit; A/D converter; ADC; CMOS technology; D/A subconvertor; S/H circuit; bandwidth enhancement; chip architecture; input capacitance; pipelined wideband sample/hold amplifier; subranging technique; subtractor; video-rate; Analog-digital conversion; Bandwidth; CMOS technology; Circuits; Degradation; Delay; Frequency conversion; Signal resolution; Voltage; Wideband;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.44983

Filename

44983