An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver´s sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-μm digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.