A multistep A/D converter family with efficient architecture

A family of 8- and 10-b analog/digital converters (ADCs) has been designed using a more efficient architecture. The 10-b ADC requires two 4-b (two 3-b for the 8-b converter) half-flash cycles and a self-corrected voltage estimator. While the speed is similar to that of conventional half-flash ADCs, power consumption and die size are lower due to reduced numbers of comparators and resistors. The flash steps can be reduced by 1 b each, for an overall reduction in comparator count by a factor of 2. This architecture can be used to reduce the comparator and resistor count of any existing half-flash ADCs, ultimately decreasing die area and power consumption. For the same process and resolution, this architecture reduces die size and power consumption by 50%