Title :
Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET´s
Author :
Su, L.T. ; Jacobs, J.B. ; Chung, J.E. ; Antoniadis, D.A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
Short-channel effects in deep-submicrometer SOI MOSFET´s are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices.
Keywords :
insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; silicon; 0.1 micron; SOI buried oxide; Si; charge-sharing; deep-submicrometer channel; depleted devices; optimal design; short-channel effects; silicon film; silicon-on-insulator MOSFETs; threshold voltage; two-dimensional numerical simulations; Doping; Jacobian matrices; MOSFET circuits; Numerical simulation; Rain; Semiconductor films; Silicon on insulator technology; Space technology; Threshold voltage; Virtual manufacturing;
Journal_Title :
Electron Device Letters, IEEE
