DocumentCode
1145736
Title
Fault Diagnosis of MOS Combinational Networks
Author
El-ziq, Yacoub M. ; Su, Stephen Y H
Author_Institution
Honeywell Corporate Computer Science Center
Issue
2
fYear
1982
Firstpage
129
Lastpage
139
Abstract
The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.
Keywords
Automatic testing; MOS (metal oxide semiconductor); computer algorithms; computer-aided testing; design for testability; diagnosable networks; fault detection; fault diagnosis; fault isolation; fault location; fault testing; statistical results; test generation; Algorithm design and analysis; Automatic testing; Computer networks; FETs; Fault detection; Fault diagnosis; Fault location; Logic design; Logic testing; Semiconductor device testing; Automatic testing; MOS (metal oxide semiconductor); computer algorithms; computer-aided testing; design for testability; diagnosable networks; fault detection; fault diagnosis; fault isolation; fault location; fault testing; statistical results; test generation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1982.1675958
Filename
1675958
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