Title :
A through-wafer interconnect in silicon for RFICs
Author :
Wu, Joyce H. ; Scholvin, Jörg ; del Alamo, Jesús A.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 μm when compared to the reference structure.
Keywords :
crosstalk; integrated circuit interconnections; radiofrequency integrated circuits; silicon; silicon compounds; system-on-chip; 10 GHz; 100 micron; 50 GHz; Faraday cage structure; RFIC; Si-Si3N4; ground inductance minimization; grounded vias; high-aspect ratio; insulating liner; interconnect technology; isolation structure; noise suppression; silicon nitride barrier liner; substrate crosstalk suppression; substrate via; system-on-chip applications; through-wafer interconnect; Crosstalk; Etching; Impedance; Isolation technology; Micromechanical devices; Radio frequency; Radiofrequency integrated circuits; Silicon; Substrates; System-on-a-chip; Ground inductance; SOC; Si RF technology; substrate noise; substrate via; system-on-chip; three-dimensional interconnects; through-wafer interconnect;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2004.837378
