Title :
A Regular Layout for Parallel Adders
Author :
Brent, Richard P. ; Kung, H.T.
Author_Institution :
Department of Computer Science, Australian National University
fDate :
3/1/1982 12:00:00 AM
Abstract :
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Keywords :
Addition; VLSI; area-time complexity; carry lookahead; circuit design; combinational logic; models of computation; parallel addition; parallel polynomial evaluation; prefix computation; Adders; Area measurement; Capacitance; Computational modeling; Computer science; Concurrent computing; Costs; Joining processes; Very large scale integration; Wire; Addition; VLSI; area-time complexity; carry lookahead; circuit design; combinational logic; models of computation; parallel addition; parallel polynomial evaluation; prefix computation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1982.1675982
