On the conduction mechanism in polycrystalline silicon thin-film transistors

Physical and electrical analyses were carried out on n-channel polycrystalline silicon thin-film transistors (nTFTs) with active regions as thin as approximately 6 nm. Such thin active regions extinguish the dominating effects of anomalous leakage and allow the conduction energy barrier height to be analyzed as a function of gate voltage in the femtoampere source/drain current regime. Grain size statistics were determined using plan view transmission electron microscopy. It is shown for the first time that in the absence of anomalous leakage, the barrier height does not decrease with decreasing gate voltage. In addition, the maximum measured barrier height is almost independent of active region thickness and grain size statistics. The source/drain current at low lateral field and high vertical field is also independent of channel length for all devices with length varied over an order of magnitude. These important discrepancies with existing TFT conduction theory are discussed within a physics-based model that addresses the effects of disorder-induced localized electron states in the bandgap. Besides describing existing data and well-known TFT behavioral trends, the model predicts a previously unknown relationship between threshold voltage variation, average threshold voltage and the number of grains in the channel. Analysis of data gathered from hundreds of devices of different dimensions across three different grain size distributions not only leads to agreement with the model but also to a remarkable universal behavior linking electrical and physical properties. This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes.