Title :
Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
Author_Institution :
Department of Applied Physics, Delft University of Technology
fDate :
4/1/1982 12:00:00 AM
Abstract :
For the realization of a bit-sequential multiplier with operands of length n, Chen and Willoner1 suggest a circuitry consisting of 2n identical modules. It is shown that if a slightly different arrangement of the modules is taken, the number of modules is reduced to n. Furthermore, the implementation in circuit form can be made more simple.
Keywords :
Computer arithmetic; on-line algorithms; parallel multiplier; pipe-lining; real-time algorithms; Circuits; Digital arithmetic; Hardware; Logic; Nonlinear filters; Signal generators; Signal processing algorithms; Technological innovation; Testing; Throughput; Computer arithmetic; on-line algorithms; parallel multiplier; pipe-lining; real-time algorithms;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1982.1676000
