A simple strategy for optimized design of one-level carry-skip adders

In this brief, a novel strategy to design carry-skip adders is proposed. It allows to distribute bits into groups to achieve minimum delay, and consists of two steps. The first is a preliminary analytical sizing based on timing considerations, the second is a successive refinement to achieve the desired number of bits. The strategy is simple, systematic and general, thus, it is helpful to design in a pencil-and-paper approach, as well as providing an in-depth understanding of the optimum group sizing. Moreover, it allows to analytically estimate the minimum delay achievable before carrying out the design. The strategy proposed has been validated by applying it to the design of more than 50 adders, varying delay of logic gates used and number of bits. Analysis confirms that the strategy provides minimum delay in practical cases.