Title :
Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems
Author :
Kaneda, Shigeo ; Fujiwara, Eiji
Author_Institution :
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation
fDate :
7/1/1982 12:00:00 AM
Abstract :
In a memory that uses byte-organized memory chips, each containing b (≥2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability.
Keywords :
Byte-organized memory chips; LSI implementation; error correcting codes; reliability; single byte error correcting– double byte error detecting codes; Circuits; Error correction codes; Hamming distance; Large scale integration; Parity check codes; Polynomials; Reed-Solomon codes; Telegraphy; Telephony; Byte-organized memory chips; LSI implementation; error correcting codes; reliability; single byte error correcting– double byte error detecting codes;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1982.1676056
