DocumentCode
1147012
Title
A study of highly scalable DG-FinDRAM
Author
Yoshida, E. ; Miyashita, T. ; Tanaka, T.
Author_Institution
Fujitsu Labs. Ltd., Akiruno, Japan
Volume
26
Issue
9
fYear
2005
Firstpage
655
Lastpage
657
Abstract
This letter reports the scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading role among other memories.
Keywords
CMOS memory circuits; DRAM chips; MOSFET; silicon-on-insulator; SOI; capacitor-less 1T-DRAM; double gate fully depleted FinFET DRAM; embedded memory; floating-body effect; gate length; retention time; scalable DG-FinDRAM; sense margin; silicon-on-insulator; Capacitors; Degradation; FinFETs; Impurities; Leakage current; MOSFET circuits; Random access memory; Scalability; Silicon on insulator technology; Voltage; DRAM; Double-gate (DG) MOSFET; FinFET; embedded memory; floating-body effect; silicon-on-insulator (SOI);
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2005.853666
Filename
1498989
Link To Document