DocumentCode :
1147033
Title :
Test counting: a tool for VLSI testing
Author :
Akers, S.B. ; Krishnamurthy, Bharadwaj
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
6
Issue :
5
fYear :
1989
Firstpage :
58
Lastpage :
77
Abstract :
The authors present a technique, called test counting, for analyzing the testing requirements imposed on a combinational network in the form of a set of stuck-at faults to be detected. By solving a large set of mathematical inequalities, called constraints, test counting determines that certain pairs of faults cannot be test simultaneously. The result is a set of mutually independence faults, no two of which can be detected by the same test vector. The number of faults becomes a lower bound on the size of the test set required. The authors provide a list of constraints to implement the test-counting algorithm and offer a complete minimal test set for the 74LS181 ALU.<>
Keywords :
VLSI; combinatorial circuits; integrated circuit testing; 74LS181 ALU; VLSI testing; combinational network; constraints; mathematical inequalities; minimal test set; mutually independence faults; stuck-at faults; test counting; testing requirements; tool; Circuit faults; Circuit testing; Controllability; Digital circuits; Fault detection; Logic testing; Observability; Process design; System testing; Very large scale integration;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.43080
Filename :
43080
Link To Document :
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