A Microprocessor-Based Technique for Detection of High Impedance Faults

Detection of high impedance faults on distribution systems is difficult due to the low current levels which flow in the fault. The objective is to detect these faults with some device or mechanism situated at the substation without modification to the distribution lines themselves. The technique presented in this paper monitors the unbalance in the fundamental, third and fifth harmonic feeder currents at the substation and performs a statistical evaluation of the present unbalance relative to past levels of unbalance. Using hypothesis testing, if the level of unbalance exceeds a threshold, a fault is indicated. The technique enploys a real-time algorithm suitable for implementation on a microprocessor-based digital relay located in the substation.