An Expression Model for Extraction and Evaluation of Parallelism in Control Structures

In the last few years advancements in VLSI technology have brought about practical research consideration of distributed computer system applications. A significant question is, "What potential improvements may be expected in an algorithm when its control structure is altered to maximize its internal parallelism?" This paper develops a general model for this area based on computation structures, defines algorithms to extract parallelism, and examines an experimental test set of programs in PL/1 to assess their potential performance improvement in expected execution time.