Optimum crystallographic alignment for Si n-channel ballistic DGFETs

Optimum intrinsic device switching time for a 7.5-nm gate-length Si n-channel double-gate field-effect transistor (DGFET) in the limit of pure ballistic transport occurs when channel quantization/transport directions are aligned to the <1 1 0>/<0 0 1> crystallographic directions, respectively. The computed switching time of 0.123 ps is 5% less than the value obtained with the more "conventional" alignment, i.e., <1 0 0>/<0 1 1>. The change in switching time versus arbitrary crystallographic alignment is fully investigated and is compared to the case of the same DGFET made from Ge.