Title :
Parallel Binary Adders with a Minimum Number of Connections
Author :
Sakura ; Muroga, Saburo
Author_Institution :
Instrumentation Division, Hitachi Ltd.
Abstract :
An n-bit parallel binary adder consisting of NOR gates only in single-rail input logic is proved to require at least 17n + 1 connections for any value of n. Such an adder is proved to require at least 7n + 2 gates. An adder that attains these minimal values is shown. Also, it is concluded that some of the parallel adders with the minimum number of NOR gates derived by Lai and Muroga have the minimum number of connections as well as the minimum number of gates, except for the two modules for the two least significant bit positions.
Keywords :
Adder with a minimum number of connections; NOR gates; logic design; minimal adder; parallel adder; ripple adder; Adders; Application software; Computer science; Concurrent computing; Costs; Logic design; Logic devices; Microprocessor chips; Minimization methods; Parasitic capacitance; Adder with a minimum number of connections; NOR gates; logic design; minimal adder; parallel adder; ripple adder;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676144
