DocumentCode
1147567
Title
Strategies for Managing the Register File in RISC
Author
Tamir, Yuval ; Sequin, Carlo H.
Author_Institution
Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California
Issue
11
fYear
1983
Firstpage
977
Lastpage
989
Abstract
The RISC (reduced instruction set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecture is a large register file which is used to minimize the overhead involved in procedure calls and returns. This paper investigates several strategies for managing this register file. The costs of practical strategies are compared with a lower bound on this management overhead, obtained from a theoretical optimal strategy, for several register file sizes.
Keywords
Cache fetch strategies; RISC; VLSI processor; computer architecture; procedure calls; register file management; Computer aided instruction; Computer architecture; Cost function; Electric variables control; High level languages; High performance computing; Pipeline processing; Reduced instruction set computing; Registers; Very large scale integration; Cache fetch strategies; RISC; VLSI processor; computer architecture; procedure calls; register file management;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1983.1676149
Filename
1676149
Link To Document