DocumentCode :
114759
Title :
PCB depanelling stress distribution simulation analysis using designated thru holes
Author :
Retnasamy, Vithyacharan ; Sauli, Zaliman ; Vairavan, Rajendaran ; Mamat, H.
Author_Institution :
Sch. of Microelectron. Eng., Univ. Malaysia Perlis (UniMAP), Arau, Malaysia
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
126
Lastpage :
129
Abstract :
This work demonstrates the evaluation of stress distribution of the printed circuit boards (PCB) during the depanelling process and technique to manage it were investigated. The stress distribution of the PCB were evaluated using 4 types of PCB geometry, one without hole, one with single front hole, one with single centric hole and one with three through holes. The holes were placed in various positions to scrutinize the stress distribution of the PCB. The PCB boards were displaced with heights in the range of 1cm till 5cm. Ansys ver 11 was utilized to perform the simulation. Key results showed that the hole structures assisted in managing the stress distribution during the arching process of the PCB subjected to its position on the PCB.
Keywords :
printed circuits; Ansys ver 11; PCB geometry; arching process; centric hole; depanelling stress distribution simulation analysis; front hole; hole structures; printed circuit boards; through holes; Analytical models; Integrated circuit modeling; Soldering; Solid modeling; Stress; Three-dimensional displays; Ansys; Depanelling process; PCB; centric hole; single hole; through hole;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Electronics (ICSE), 2014 IEEE International Conference on
Conference_Location :
Kuala Lumpur
Type :
conf
DOI :
10.1109/SMELEC.2014.6920812
Filename :
6920812
Link To Document :
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