Low-Leakage Storage Cells for Ternary Content Addressable Memories

Innovative architectural and circuit techniques are reducing the dynamic power in ternary content addressable memories (TCAMs). Also, shrinking device dimensions are making transistors increasingly leaky. Due to these two trends, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 40% leakage reduction over the conventional TCAM cell at the expense of a small degradation (<8%) in the static noise margin (SNM). The SNM degradation is negligible (<1%) for lower power supply voltages (<0.8 V). Measurement results of a test chip in 0.18-mum CMOS technology demonstrate that the proposed cells can perform read and write operations in less than 3.6 ns.