DocumentCode
1147820
Title
On the Acceleration of Test Generation Algorithms
Author
Fujiwara, Hideo ; Shimono, Takeshi
Author_Institution
Department of Electronic Engineering, Osaka University
Issue
12
fYear
1983
Firstpage
1137
Lastpage
1144
Abstract
In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.
Keywords
Combinational logic circuits; D-algorithm; PODEM algorithm; decision tree; multiple backtrace; sensitization; stuck faults; test generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Life estimation; Logic circuits; Logic testing; Performance evaluation; System testing; Combinational logic circuits; D-algorithm; PODEM algorithm; decision tree; multiple backtrace; sensitization; stuck faults; test generation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1983.1676174
Filename
1676174
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