Process-induced NBTI-imbalance of high-k/metal-gate deep-submicron CMOS

Negative bias temperature instability (NBTI) is a critical reliability concern for deep-submicron high-k metal-gate p-MOSFETs. This paper reports the impact of aggressive junction-depth scaling with laser spike annealing (LSA) superactivation on NBTI-imbalance. The testbed device simulated in this work incorporates advanced process steps of shallow trench isolation (STI) with intrinsic stress, high-k metal gate, dipole charge, stress engineering with epi-SiC and epi-SiGe pockets and dual stress liner (DSL) on-state drain current improvements for gate-first CMOS processing. The results indicate that as the laser annealing decreases and dielectric thickness increases, the drain current would be further reduced. The increase of 100 °C in laser spike annealing temperature yields ~2 to 5 times leakage reduction. It is also investigated that thin HfO₂ layers with lower barrier energy leads to higher and faster occupation of the charged trap state during charging phase. Energy transition from E´ center to neutral precursors state with lower LSA temperature leads to a lower occupation of the charged trap, thus responsible for faster neutralization. A correlation of the time dependency for the charged trap concentration, interfacial density and the drain current is observed with ~10% remarkable current degradation due to the trap accumulation. The measured ΔVth reduced for higher laser-induced high activation of the dopant thus is considered for the evaluation of the device performance.