Title :
Loop based design for wafer scale systems
Author :
Pelletier, R.V. ; McLeod, R.D.
Author_Institution :
Bell-Northern Res., Ottawa, Ont., Canada
Abstract :
This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models.<>
Keywords :
VLSI; cellular arrays; circuit layout CAD; circuit reliability; fault tolerant computing; microprocessor chips; parallel architectures; loop based design; nonplanar graph; percolation models; reconfiguration algorithms; wafer scale systems; Algorithm design and analysis; Context modeling; Fault tolerant systems; Hardware; Multiplexing; Nearest neighbor searches; Propagation delay; Semiconductor device modeling; Topology; Two dimensional displays;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
