Title :
A Tree Representation of Combinational Networks
Author :
Chiang, Kuang-wei ; Vranesic, Zvonko G.
Author_Institution :
Department of Electrical Engineering and Computer Science, University of Toronto
fDate :
3/1/1983 12:00:00 AM
Abstract :
A tree representation of a combinational network is developed. An algorithm is proposed for finding the functional expression realized by the network. The tree representation has storage requirement linear with respect to the number of input-output paths in the network. It is shown that rmding the complementary function and generating network SPOOF can be performed efficiently on the tree structure.
Keywords :
Combinational network model; fault detection; logic circuits; testing; Circuit faults; Circuit testing; Computer networks; Councils; Electrical fault detection; Intelligent networks; Logic circuits; Logic testing; Predictive models; Tree data structures; Combinational network model; fault detection; logic circuits; testing;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1983.1676224
