Implementation of low power compressed ROM for direct digital frequency synthesizer

Author

Alkurwy, Salah Hasan ; Md Ali, Sawal Hamid ; Islam, Md Shariful

Author_Institution

Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia

fYear

2014

fDate

27-29 Aug. 2014

Firstpage

309

Lastpage

312

Abstract

A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.

Keywords

direct digital synthesis; logic gates; matrix decomposition; power consumption; read-only storage; table lookup; XOR logic gate; angular decomposition technique; direct digital frequency synthesizer; frequency 0.029 Hz; frequency resolution; look-up table; low power compressed ROM implementation; low power consumption; quarter wave symmetry technique; sine wave; sine-cosine symmetrical attribute; storage capacity 12 bit; storage capacity 368 bit; subROM block; trigonometric identity; Adders; Approximation methods; Clocks; Frequency synthesizers; Geometry; Read only memory; Table lookup; ROM Look-up table (ROM LUT); direct digital frequency synthesizer (DDFS); phase accumulator (PA);

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics (ICSE), 2014 IEEE International Conference on

Conference_Location

Kuala Lumpur

Type

conf

DOI

10.1109/SMELEC.2014.6920859

Filename

6920859