DocumentCode :
1148536
Title :
Concurrent Error Detection in Multiply and Divide Arrays
Author :
Patel, Janak H. ; Fung, Leona Y.
Author_Institution :
Coordinated Science Laboratory and the Department of Electrical Engineering, University of Illinois
Issue :
4
fYear :
1983
fDate :
4/1/1983 12:00:00 AM
Firstpage :
417
Lastpage :
422
Abstract :
A method proposed for concurrent error detection in ALU´s is used in the design of multiplier and divider arrays. This method, called recomputing with shifted operands (RESO), can detect all errors caused by failures confined to a cell of the cellular array. The assumption that the failures are confined to a small area of an integrated circuit and the precise nature of the failures is not known is very applicable to VLSI circuits. RESO uses time redundancy for error detection and requires only a small increase in the hardware of a multiply and divide array.
Keywords :
Cellular logic; RESO; concurrent error detection; dividers; multipliers; Circuit faults; Combinational circuits; Computer errors; Digital arithmetic; Fault tolerant systems; Hardware; Integrated circuit interconnections; Logic; Redundancy; Very large scale integration; Cellular logic; RESO; concurrent error detection; dividers; multipliers;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1983.1676246
Filename :
1676246
Link To Document :
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