Low power and low voltage SRAM design for LDPC codes hardware applications

Author

Deena Kumari Selvam, Rosalind ; Senthilpari, C. ; Lee Lini

Author_Institution

Fac. of Comput. & Inf., Multimedia Univ., Cyberjaya, Malaysia

fYear

2014

fDate

27-29 Aug. 2014

Firstpage

332

Lastpage

335

Abstract

The Low Voltage Low Power (LVLP) 8T, 11T, 13T and ZA SRAM cell is designed using the dynamic logic SRAM cell. The SRAM cells are implemented using pass transistor logic technique, which is mainly focused on read and write operation. The circuits are designed by using DSCH2 circuit editor and their layouts are generated by MICROWIND3 layout editor. The Layout Versus Simulation (LVS) design has been verified using BSIM 4 with 65nm technology and with a corresponding voltage of 0.7V respectively. The simulated SRAM layouts are verified and analyzed. The SRAM 8T gives power dissipation of 0.145 microwatts, propagation delay of 37.2 pico seconds, area of 14 × 8 micrometers and a throughput of 4.037 nano seconds.

Keywords

SRAM chips; integrated circuit design; logic circuits; low-power electronics; parity check codes; transistor circuits; 11T ZA SRAM cell; 13T SRAM cell; 8T SRAM cell; BSIM 4; DSCH2 circuit editor; LDPC code hardware; LVS design; MICROWIND3 layout editor; ZA SRAM cell; dynamic logic SRAM cell; layout versus simulation design; low power SRAM design; low voltage SRAM design; pass transistor logic technique; power 0.145 muW; power dissipation; read-write operation; size 65 nm; time 4.037 ns; voltage 0.7 V; Clocks; Delays; Integrated circuit modeling; Power dissipation; SRAM cells; Transistors; SRAM cell; delay; power dissipation; throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics (ICSE), 2014 IEEE International Conference on

Conference_Location

Kuala Lumpur

Type

conf

DOI

10.1109/SMELEC.2014.6920865

Filename

6920865