• DocumentCode
    1148721
  • Title

    Bus-driven floorplanning

  • Author

    Xiang, Hua ; Tang, Xiaoping ; Wong, Martin D F

  • Author_Institution
    Cadence Design Syst. Inc., San Jose, CA, USA
  • Volume
    23
  • Issue
    11
  • fYear
    2004
  • Firstpage
    1522
  • Lastpage
    1530
  • Abstract
    In this paper, we present an integrated approach for floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus specifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a placement of all circuit blocks such that each bus can be realized as a rectangular strip (horizontal or vertical) going through all the blocks connected by the bus. The objective is to determine a feasible BDF solution that minimizes the floorplan area and the total bus area. Our approach is based upon the sequence-pair floorplan representation. After a careful analysis of the relationship between bus ordering and block ordering in the floorplan represented by a sequence pair, we derive feasibility conditions on sequence pairs that give feasible BDF solutions. Experimental results demonstrate the efficiency and effectiveness of our algorithm.
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; block ordering; bus ordering; bus planning; bus specifications; bus-driven floorplanning; circuit blocks; computer aided design; sequence-pair floorplan representation; very large scale integration; Circuits; Design automation; Routing; Strips; Very large scale integration; 65; CAD; Computer-aided design; VLSI; floorplan; physical design; sequence pair; very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2004.836728
  • Filename
    1350879