A monolithic processing subsystem

Author

Brewer, Joe E. ; Miller, L. Gray ; Gilbert, Ira H. ; Melia, Joseph F. ; Garde, Douglas ; DeMaris, James E.

Author_Institution

Westinghouse Electr. Corp., Baltimore, MD, USA

Volume

17

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

310

Lastpage

317

Abstract

A single-chip 120 MFLOP (peak) 26 million transistor digital processing subsystem with 512 kilobytes of on-chip SRAM has been developed. This general purpose 32-bit floating point Harvard architecture device, which incorporates sophisticated communication capabilities and at maximum throughput dissipates less than 2 W, can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arrays. This paper describes physical and functional features of the chip, and provides some discussion of how it can be applied

Keywords

CMOS integrated circuits; digital arithmetic; digital signal processing chips; parallel architectures; 120 MFLOPS; 32 bit; CMOS; MIMD processor arrays; SIMD processor arrays; floating point Harvard architecture; maximum throughput; on-chip SRAM; single-chip digital processing subsystem; stand-alone processor; Associate members; CMOS process; High performance computing; Integrated circuit technology; Laboratories; Parallel machines; Process control; Production; Random access memory; Throughput;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1070-9894

Type

jour

DOI

10.1109/96.311779

Filename

311779