A dynamic clock synchronization technique for large systems

This paper reports on a circuit technique which can be used to reduce the clock skew in ULSI and WSI systems. It is suitable for large systems which are divided into isochronic modules with locally optimized clock distribution. The inter-module clock distribution uses tunable delay elements to compensate for the differences in the phase delay of the individual modules. The delay elements introduce a phase shift to the clock signals going to each region to align the clock edges at the leaves of the local clock trees. This technique is dynamic in the sense that it guarantees clock synchronization in the presence of process or ambient variations. Whenever the clock skew exceeds a specific limit, the clock synchronization systems is activated to restrain the skew. The advantage of this technique over using phase locked loop circuits is that it saves power consumption and area. In addition, its lock-in time is much shorter. Experiments have shown that using the tunable delay element approach is capable of reducing the skew to less than 100 ps. A stability criterion was developed. The effect of substrate and power supply noise on the synchronization scheme was also investigated