An architectural approach for increasing clock frequency and communication speed in monolithic WSI systems

Based on a special pipelining technique, a new methodology for increasing the clock frequency and communication speed in monolithic WSI systems is proposed. SPICE simulations show that the clock frequency on a synchronous wafer-scale system, implemented using a 1.2 μm CMOS technology, can be operated well above 140 MHz, which is approximately five times the maximum frequency of current systems. It is also shown that frequencies higher than 1 GHz can be achieved if the technique is pushed to its limits. The methodology can be applied to interconnection networks as well, thereby improving their speed by approximately the same factor. In order to assess the various design tradeoffs imposed by the technique, a prototype communication interface has been designed using 1.2 μm CMOS standard cells. This interface is intended to be used in a special distributed-queue, dual-bus (DQDB) communication network