• DocumentCode
    1149571
  • Title

    Input Variable Assignment and Output Phase Optimization of PLA´s

  • Author

    Sasao, Tsutomu

  • Author_Institution
    Department of Electronic Engineering, Osaka University
  • Issue
    10
  • fYear
    1984
  • Firstpage
    879
  • Lastpage
    894
  • Abstract
    A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA´s and PLA´s with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.
  • Keywords
    Adder; complexity of logic circuits; decoder assignment; essential prime implicants; logic design; output phase optimization; programmable logic array; switching theory; Arithmetic; Decoding; Design methodology; Input variables; Logic circuits; Logic design; Minimization; Phase detection; Phased arrays; Programmable logic arrays; Adder; complexity of logic circuits; decoder assignment; essential prime implicants; logic design; output phase optimization; programmable logic array; switching theory;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1984.1676349
  • Filename
    1676349
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1149571