DocumentCode
1149808
Title
Packet Switching Networks for Multiprocessors and Data Flow Computers
Author
Chin, Chi-yuan ; Hwang, Kai
Author_Institution
Corporate Research and Development, General Electric Company
Issue
11
fYear
1984
Firstpage
991
Lastpage
1003
Abstract
Most packet switched multistage networks have been proposed to use a unique path between any source and destination. We propose to add a few extra stages to create multiple paths between any source and destination. Connection principles of such multipath networks for packet switching are presented. Performance of such networks is analyzed for possible use in multiprocessor systems or in data flow computers.
Keywords
Arbitration network; buffered 2-by-2 switches; data flow computers; distribution network; interprocessor-memory networks; multiprocessor systems; multistage interconnection network; packet switching; Computer networks; Data flow computing; Delay; Distributed computing; Multiprocessing systems; Multiprocessor interconnection networks; Packet switching; Performance analysis; Switches; Telecommunication traffic; Arbitration network; buffered 2-by-2 switches; data flow computers; distribution network; interprocessor-memory networks; multiprocessor systems; multistage interconnection network; packet switching;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1984.1676373
Filename
1676373
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