A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors

A physical model considering the effects of grain boundaries on the turn-on behavior of polysilicon thin-film transistors (poly-Si TFTs) is presented. Along the channel, the formation of the potential barrier near the grain boundary is proposed to account for the low transconductance and high turn-on voltage of TFTs. The barrier height is expressed in terms of channel doping, gate oxide thickness, grain size, and external gate as well as drain biases. Drain bias results in an asymmetric potential barrier and introduces more carrier injection from the lowered barrier side. It is shown that this consideration is very important for characterizing the saturation region under large drain-bias conditions. On the basis of the developed potential barrier model, the I-V characteristics are described by the interfacial-layer thermionic-diffusion model. Thin-film transistors on polycrystalline silicon with a coplanar structure were fabricated for testing. Comparisons show excellent agreement between the developed model and the experimental data