An EPROM cell structure for EPLDs compatible with single poly-Si gate process

A single poly-Si gate EPROM cell structure, which can eliminate the process complexity involved in conventional double poly-Si EPROM technologies, is proposed to realize erasable programmable logic devices (EPLDs) with faster turnaround time. Since the proposed cell uses an n ⁺ diffused layer on a bulk Si substrate as a control gate instead of a second poly-Si, improved reliability is obtained, especially for bias stress data retention. This is because bulk Si oxide has a higher quality than an interpoly insulator of double-poly EPROMs. Basic cell characteristics (write, erase, I-V, high-temperature data retention, etc.) are almost the same as those for a double-poly cell. It was found that the single-poly cell is easily combined with the single-poly and double-metal process for logic devices. Therefore, it should greatly contribute to developing CMOS EPLDs in spite of the cell area increase