Title :
Dual-modulus frequency dividers with minimum gate count
Author_Institution :
Semiconductor Product Sector, Motorola Inc., Tempe, AZ
fDate :
7/21/1994 12:00:00 AM
Abstract :
A method for minimising the gate count in dual-modulus frequency dividers is presented. The gate count is minimised by identification of a set of Boolean equations with one type of Boolean operator only, using internal gates of D-flipflops to realise the Boolean functions. Circuit diagrams for divide-by-2/3 and divide-by-4/5 static frequency dividers are shown. The minimised circuits have higher speed and lower power consumption compared to conventional solutions because additional gates are not required
Keywords :
Boolean functions; flip-flops; frequency dividers; logic design; minimisation of switching nets; sequential circuits; Boolean equations; Boolean functions; D-flipflops; dual-modulus frequency dividers; identification; minimum gate count; static frequency dividers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940829
