DocumentCode :
1150448
Title :
Systolic Multipliers for Finite Fields GF(2m)
Author :
Yeh, C.-S. ; Reed, Irving S. ; Truong, T.K.
Author_Institution :
Department of Electrical Engineering, University of Southern California
Issue :
4
fYear :
1984
fDate :
4/1/1984 12:00:00 AM
Firstpage :
357
Lastpage :
360
Abstract :
Two systolic architectures are developed for performing the product–sum computation AB + C in the finite field GF(2m) of 2melements, where A, B, and C are arbitrary elements of GF(2m). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The first multiplier requires a smaller number of basic cells than the second multiplier. The second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively. To perform single computations both multipliers require the same computational time. In both cases the architectures are simple and regular and possess the properties of concurrency and modularity. As a consequence they are well suited for use in VLSI systems.
Keywords :
Finite field; logic design; primitive element; systolic array; Algorithm design and analysis; Arithmetic; Circuits; Computer architecture; Concurrent computing; Galois fields; Polynomials; Signal processing algorithms; Systolic arrays; Very large scale integration; Finite field; logic design; primitive element; systolic array;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1984.1676441
Filename :
1676441
Link To Document :
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