• DocumentCode
    1150632
  • Title

    A Loop-Structured Switching Network

  • Author

    Wong, F.S. ; Ito, M.R.

  • Author_Institution
    Department of Electrical Engineering, University of British Columbia
  • Issue
    5
  • fYear
    1984
  • fDate
    5/1/1984 12:00:00 AM
  • Firstpage
    450
  • Lastpage
    455
  • Abstract
    This paper describes a novel loop-structured switching network (LSSN) intended for highly parallel processing architectures. With L loops, it can connect up to N = L* log2 L pairs of transmitting and receiving devices using only N/2 two-by-two switching elements; thus, it is very cost-effective in terms of its component count. Its topology resembles that of the indirect binary n-cube network, but a much higher device-to-switch ratio is achieved because all the links between the switches could be used as both transmitting and receiving stations. It has the advantage of incremental extensibility, and-it could avoid store-and-forward deadlocks (SFD) which prevail in other recirculating packet-switched networks. Our simulation studies show that the average throughput rate and delay of LSSN are close to that of other designs despite its relatively low component count.
  • Keywords
    Deadlock avoidance methods; packet switching; parallel processing architectures; recirculating networks; Communication switching; Computational modeling; Feedback loop; Indium tin oxide; Large-scale systems; Network topology; Parallel processing; Switches; System recovery; Transmitters; Deadlock avoidance methods; packet switching; parallel processing architectures; recirculating networks;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1984.1676462
  • Filename
    1676462